1. Field of the Invention
The present invention relates to a display driving apparatus, and more specifically to an apparatus for driving a visual display panel, such as a liquid crystal display (LCD) panel. The present invention also relates to a method of driving such a display panel.
2. Description of the Background Art
Conventionally, in a display driving apparatus, e.g. for driving a LCD panel of TFT (Thin-Film Transistor) type, switches are provided to pre-charge the pixel electrodes of the LCD panel to a required potential level by temporarily short-circuiting the pixel electrodes so that the gradation voltages applied to the pixel electrodes are charged and then discharged at high-speed to perform high-speed dot-inversion driving of the LCD panel. As such a display driving apparatus, various apparatuses have been proposed.
For instance, U.S. patent application publication No. US 2007/0171169 A1 to Hirama discloses a display driving apparatus, which is able to prevent inner heat generation by means of pre-charging done from the external power supply.
In the display driving apparatus disclosed in Hirama, an operational amplifier outputs gradation voltages corresponding to image data and the output voltages are pre-charged by the external power supply at predetermined timing, i.e. a charge-sharing manner is performed so that heat generation is suppressed.
Recently, image data tends to be generated with longer bit length as well as higher resolution/definition. For instance, a decoder used for generating image data comprises a ladder circuit composed of a plurality of resistors serially connected, the ladder circuit outputs a plurality of multilevel gradation voltages and then the decoder selects a required graduation voltage corresponding to the applied image data from the gradation voltages to supply the selected voltage to the operational amplifier. As such a decoder, a decoder composed of multistage-connected switching elements, such as MOS-FETs (Metal Oxide Semiconductor-Field Effect Transistors), is used. For instance, a tournament-like arranged decoder as disclosed in U.S. patent application publication No. US 2008/0106318 A1 to Uchida is used for above-mentioned display driving apparatuses. In such cases, the number of stages of the serially connected switch elements constituting a decoder increases as the number of bits of image data increases. Therefore, the ON-resistance value of a transistor for use in the switching element, such as MOS-FET, is increased.
Furthermore, in recent years, as multi-channelization has been developed, the number of required outputs from the source driver exceeds 500 channels and approaches 1,000 channels. For example, if image data consists of the same data on each channel, the same gradation voltages are supplied to all of the channels from a single ladder circuit. Therefore, when the decoder and the input gate of the operational amplifier required for all of the channels have the respective loads, there are problems that the outputs of the decoder are delayed and then the voltages cannot reach a target potential level during the sampling period.
Recently, as the higher speed displays have been developed, the shorter sampling period is required and hence the pre-charging period is shortened. However, when the number of switching stages of the decoder is increased and consequently the ON-resistance value thereof is also increased, it may be impossible to heighten the positive-going speed of the voltage in the decoder to the extent of the speed of pre-charging. In this case, after the pre-charging period has finished, the output voltage may be temporarily fallen. These therefore cause problems that the voltage does not reach the target potential level before the sampling period has finished.